The present invention relates to a semiconductor memory device, and more particularly to a data output buffer of a semiconductor memory device using an external clock having a fixed period from outside.
In general, since a semiconductor memory device such as a DRAM (Dynamic Random Access Memory) basically inputs a row address strobe signal RAS generated externally of the chip, it is possible to perform a data read operation or a data write operation. Namely, after the row address strobe signal RAS had been enabled and a predetermined time passes, if a column address strobe signal CAS is output, the period when data is output from the chip is constant.
FIG. 1 shows a data output buffer of a semiconductor memory device. The semiconductor memory device shown in FIG. 1 includes an inverter 35 for receiving external clock CLK input from the out of the chip, an inverter 40 for again inverting the output signal of the inverter 35, and transfer gates 5 and 55 controlled by the output signals of the inverters 35 and 40. Data DO and DO are input to the transfer gates 5 and 55 from a sense amplifier (not shown). Each of output signals of the transfer gates 5 and 55 of data input 90 is temporarily stored in latches 85 and 97 and is then transferred to drivers 95 and 100. A pull-up transistor 25 of the driver 95 of the data DO, uses as power a boost voltage VPP boosted within the semiconductor memory device so that a pull-up transistor 30 for output enables a power supply voltage VCC to be supplied to a data output node N1 by raising the potential of the gate terminal of pull-up transistor 30 above VCC voltage.
FIG. 2 is a timing diagram of the FIG. 1 circuit. In FIG. 2, the system clock CLK provided from the outside is successively generated. After the column address strobe signal CAS is enabled, a second clock is enabled to a logic "high" state from a logic "low" state and a data output buffer enable signal .phi.TRST is thus enabled to the logic "high" state. Thereby, a first data is output and the data output buffer is thus enabled. Since the time required in enabling the data output buffer enable signal .phi.TRST is delayed, a delay time exits before the data output buffer is enabled, the result being that the speed of the data output operation becomes low. However, since the data output buffer enable signal .phi.TRST is maintained at the logic "high" state, data following a second data correspond to clocks following a fourth clock, respectively and then are generated.
In the meantime, in the data output buffer of the semiconductor memory device shown in FIG. 1, if the output buffer enable signal .phi.TRST is varied, the variation should affect an output operation of the effective data.
In the semiconductor memory device operating in synchronization with the system clock having an externally fixed period the point of time for enabling the data output buffer is important to properly output the effective data from the data output buffer. Further, in a system operable according to the frequency of the system clock, the period of the clock is changed according to the frequency thereof to thereby enable the data output buffer enable signal .phi.TRST.